Since lateral PNP transistors in conventional bipolar integrated circuit manufacturing processes have very limited speed and current capabilities, it is a common practice to provide wideband micropower operational amplifiers with output stages having only NPN transistors in the main signal path. See, for example, U.S. Pat. No. 4,403,200 and the paper "A 1-GHz Bipolar Class-AB Operational Amplifier with Multipath Nested Miller Compensation for 76-dB Gain", by Klaas-Jan de Langen et al., IEEE Journal of Solid-State Circuits, Vol. 32, No. 4, April, 1997. U.S. Pat. No. 4,403,200 discloses an NPN output stage in which a current source 30 must be large enough to allow pull-up transistor 24 to supply the largest possible expected load current. Consequently, the quiescent current is very large, and the power dissipation of the output stage is higher than desirable.
This is one main drawback of existing solutions involving use of only NPN transistors in the main signal path. Another drawback is that attempts to supply the largest expected load current by using Darlington transistors to increase the current gain results in unacceptably large saturation voltages of the pull-down transistors of the output stage. This technique therefore is not useful in low voltage and micropower operational amplifiers. In the closest prior art micropower operational amplifier, the maximum ratio of the peak output current to the quiescent current is limited to approximately 50. Furthermore, it is desirable that the quiescent current (i.e., the current with the input signal equal to zero volts) of a micropower amplifier be stable so that variations in the quiescent current do not produce non-linearities in the output signal and that the operational amplifier be capable of driving a large capacitive load.
FIG. 1 of U.S. Pat. No. 4,853,645 by Seevinick et al., entitled "AMPLIFIER ARRANGEMENT WITH QUIESCENT CURRENT CONTROL", discloses an amplifier arrangement wherein the first output transistor T.sub.1 and a second output transistor T.sub.2 are push-pull transistors driven by a drive circuit 10 having two transistors T.sub.11 and T.sub.12 which have current sources T.sub.13 and T.sub.14 respectively, as load devices. Currents which are a measure of the currents flowing through the first output transistor T.sub.1 and the second output transistor T.sub.2 are generated by a first current measuring circuit 20 and a second current measuring circuit 30. These currents are applied to a negative feedback circuit 40 which controls the intensity of the current sources T.sub.13 and T.sub.14 in such a way that the harmonic mean value of the currents flowing through the first output transistor T.sub.1 and the second output transistor T.sub.2 is substantially equal to a reference value. A drawback of this circuit is that it has a large quiescent current. Also, the constant current source I4 in FIG. 1 of the Seevinick et al. patent must be large enough to supply all of the base current ever needed by the pull-up transistor T1 and the pull-down transistor T2 during any transient. For this reason alone is the Seevinick et al. circuit not suitable for very low power applications. Also, the maximum output voltage is approximately 2.5 V.sub.BE voltage drops lower than the positive supply voltage, undesirably limiting the output voltage range.
There is an unmet need for a very low power, wideband operational amplifier push-pull output stage with a lower, more stable quiescent current than has previously been achieved.